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ICS94201 数据表(PDF) 10 Page - Integrated Circuit Systems

部件名 ICS94201
功能描述  Programmable System Frequency Generator for PII/III?
PDF  18 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS94201 数据表(HTML) 10 Page - Integrated Circuit Systems

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10
ICS94201
Byte 21: ICS Reserved Register
Byte 23: Group Skew Control Register
Byte 22: Group Skew Control Register
Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001.
Each increment or decrement of bit 4 to 7 will
introduce 100ps delay or advance on all PCI
clocks.
Byte 24: Output Rise/Fall Time Select Register
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Byte 20: Output Dividers Control Register
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the hardware
(latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-24 will lose their default power up value.
Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111.
Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all IOAPIC clocks.
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