4

ICS94201

Notes:

1.

verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined

by writing to byte 6.

2.

When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte

14 is written but not 15, neither byte 14 or 15 will load into the receiver.

3.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

4.

The input is operating at 3.3V logic levels.

5.

The data byte format is 8-bit bytes.

6.

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

7.

At power-on, all registers are set to a default condition, as shown.

Register Name

Byte

Description

Pwd Default

Functionality & Frequency Select

Register

0

select, spread spectrum & output enable

control register.

See individual byte

des cription

Output Control Registers

1-5

Active / inactive output control registers.

See individual byte

des cription

Byte Count Read Back Register

6

W riting to this register will configure byte

count and how many byte will be read back.

Latched Inputs Read Back

Register

7

The inverse of the latched inputs level could

be read back from this register.

See individual byte

des cription

W atchdog Control Registers

8 Bit[6:0]

W atchdog enable, watchdog status and

programmable 'safe' frequency' can be

configured in this register.

000,0000

VCO Control Selection Bit

8 Bit[7]

This bit selects whether the output

frequency is controled by hardware/byte 0

configurations or byte 14&15 programming.

0

W atchdog Timer Count Register

9

W riting to this register will configure the

number of seconds for the watchdog timer

to reset.

ICS Reserved Register

10

This is an unused register. W riting to this

register will not affect device functionality.

Device ID, Vendor ID & Revision ID

Registers

11-12

Byte 11 bit[3:0] is ICS vendor id - 0001.

Other bits in these 2 registers designate

device revision ID of this part.

See individual byte

des cription

ICS Reserved Register

13

Don't write into this register, writing 1's will

cause malfunction.

VCO Frequency Control Registers

14-15

These registers control the dividers ratio

into the phase detector and thus control the

VCO output frequency.

Depend on

hardware/byte 0

configuration

Spread Spectrum Control

Registers

16-17

These registers control the spread

percentage amount.

Depend on

hardware/byte 0

configuration

Output Dividers Control Registers

18-20

Changing bits in these registers result in

frequency divider ratio changes. Incorrect

configuration of group output divider ratio

can cause system malfunction.

Depend on

hardware/byte 0

configuration

Group Skews Control Registers

21-23

Increment or decrement the group skew

amount as compared to the initial skew.

See individual byte

des cription

Output Rise/Fall Time Select

Registers

24

These registers will control the group rise

and fall time.

See individual byte

des cription

Brief I

Programmable System Frequency Generator