USB5734 datasheet(35/61 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS00001854D-page 35

USB5734

7.4

Two Pin Serial Port (UART) Interface

The device incorporates a fully programmable, universal asynchronous receiver/transmitter (UART) that is functionally

compatible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel

conversion on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are

provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are

available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are

programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,

odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capa-

ble of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI

data rate.

7.4.1

TRANSMIT OPERATION

Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is

then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in

the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,

Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.

If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if

enabled) becomes empty.

When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for

transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data

is indicated by interrupt.

7.4.2

RECEIVE OPERATION

Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the

Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.

When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or

to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this reg-

ister.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.

If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-

ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal

RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.

When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received

data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when

the RX FIFO contains 1, 4, 8 or 14 bytes of data.

Note:

Extensions to the I2C Specification are not supported.

All device configuration must be performed via the Pro-Touch Programming Tool. For additional information

on the Pro-Touch programming tool, contact your local sales representative.

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