L6986 datasheet(48/68 Pages) STMICROELECTRONICS

48 / 68 page

Application notes

L6986

48/68

DocID025376 Rev 7

The master driving capability must be able to provide the proper signal levels at the SYNCH

pin (see Table 5 on page 8 - Synchronization section):

 Low level < VSYN THL= 0.7 V sinking 5 mA

 High level > VSYN THH = 1.2 V sourcing 0.7 mA

Figure 37. Master driving capability to synchronize the L6986

As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the

slope compensation is dimensioned accordingly with FSW resistors so, even if the L6986

supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit

the switching operation around a working point close to the selected frequency (FSW

resistor).

As a consequence, to guarantee the full output current capability and to prevent the

subharmonic oscillations the master must limit the driving frequency range within ± 20% of

the selected frequency.

A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the

peak current capability (see IPK parameter in Table 5) since the internal slope compensation

signal may be saturated.

Since the slope compensation contribution, that is required to prevent subharmonic

oscillations in peak current mode architecture, depends on the switching frequency, it is

important to select the same switching frequency for all regulators (all of them operate as

SLAVE) one step lower than the reference signal (please refer to Table 6: fSW selection on

page 11). As a consequence, all the regulators have the same resistor connected to the

FSW pin.

In order to guarantee the synchronization as a slave over distribution, temperature and the

output load, the external clock frequency must be lower than 1.4 MHz.

VSYN_TH_H

VSYN_TH_L

VCCM

5 mA

0.7 mA

L6986 数据表(PDF) 48 Page - STMicroelectronics