DS17885 datasheet(18/38 Pages) DALLAS

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DS17885/DS17887

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A kickstart sequence occurs when kickstarting is enabled through KSE = 1. While the system is powered

down, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When

such a transition is detected, the PWR line is pulled low, as it is for a wake-up condition. Also at this

time, the kickstart Flag (KF, bank 1, register 04AH) is set, indicating that a kickstart condition has

occurred.

The timing associated with both the wake-up and kickstarting sequences is illustrated in the

Wake-Up/Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing

associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram.

The occurrence of either a kickstart or wake-up condition causes the PWR pin to be driven low, as

described above. During interval 1, if the supply voltage on the DS17885/DS17887 VCC pin rises above

the greater of VBAT or VPF before the power-on timeout period (tPOTO) expires, then PWR remains at the

active low level. If VCC does not rise above the greater of VBAT or VPF in this time, then the PWR output

pin is turned off and returns to its high-impedance level. In this event, the IRQ pin also remains tri-stated.

The interrupt flag bit (either WF or KF) associated with the attempted power-on sequence remains set

until cleared by software during a subsequent system power-on.

If VCC is applied within the timeout period, then the system power-on sequence continue as shown in

intervals 2 to 5 in the timing diagram. During interval 2, PWR remains active and IRQ is driven to its

active low level, indicating that either WF or KF was set in initiating the power-on. In the diagram KS is

assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit is automatically cleared to 0

in response to a successful power-on. The PWR line remains active as long as the PAB remains cleared to

At the beginning of interval 3, the system processor has begun code execution and clears the interrupt

condition of WF and/or KF by writing 0’s to both of these control bits. As long as no other interrupt

within the DS17885/DS17887 is pending, the IRQ line is taken inactive once these bits are reset.

Execution of the application software can proceed. During this time, both the wake-up and kickstart

functions can be used to generate status and interrupts. WF is set in response to a date, hours, minutes,

and seconds match condition. KF is set in response to a low-going transition on KS . If the associated

interrupt-enable bit is set (WIE and/or KSE), then the IRQ line is driven active low in response to enabled

event. In addition, the other possible interrupt sources within the DS17885/DS17887 can cause IRQ to be

driven low. While system power is applied, the on-chip logic always attempts to drive the PWR pin active

in response to the enabled kickstart or wake-up condition. This is true even if PWR was previously

inactive as the result of power being applied by some means other than wake-up or kickstart.

The system can be powered down under software control by setting the PAB bit to a logic 1. This causes

the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in

the timing diagram. As VCC voltage decays, the IRQ output pin is placed in a high-impedance state when

VCC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart, then

the both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to setting

the PAB bit.

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