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DS17885 数据表(PDF) 28 Page - Dallas Semiconductor |
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DS17885 数据表(HTML) 28 Page - Dallas Semiconductor |
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28 / 38 page  DS17885/DS17887 28 of 38 RTC AC TIMING CHARACTERISTICS Over the operating range (5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle Time tCYC 240 DC ns Pulse-Width, RD / WR Low PWRWL 120 ns Pulse-Width, RD / WR High PWRWH 80 ns Input Rise and Fall Time tR, tF 30 ns Chip-Select Setup Time before WR or RD tCS 20 ns Chip-Select Hold Time tCH 0ns Read Data Hold Time tDHR 10 50 ns Write Data Hold Time tDHW 0ns Muxed Address Valid Time to ALE Fall tASL 20 ns Muxed Address Hold Time to ALE fall tAHL 10 ns RD or WR High Setup to ALE Rise tASD 25 ns Pulse-Width ALE High PWASH 40 ns ALE Low Setup to RD or WR Fall tASED 30 ns Output Data-Delay Time from RD tDDR 20 120 ns 6 Data Setup Time tDSW 30 ns IRQ Release from RD tIRD 2 ms AC TEST CONDITIONS Output Load: 50pF Input Pulse Levels: 0V to 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns |
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