6.42

IDT71321SA/LA and IDT71421SA/LA

High Speed 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

16

being expanded in depth, then the

BUSYindicationfortheresultingarray

does not require the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

WhenexpandinganSRAMarrayinwidthwhileusing

BUSYlogic,one

master part is used to decide which side of the SRAM array will receive

a

BUSYindication,andtooutputthatindication.Anynumberofslavesto

be addressed in the same address range as the master, use the

BUSY

signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs

the

BUSYpinisanoutputifthepartisMaster(IDT71321),andtheBUSY

pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decision could result with one master indicating

BUSYononesideofthe

array and another master indicating

BUSYononeothersideofthearray.

This would inhibit the write operations from one port for part of a word and

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The

BUSY arbitration, on a Master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughfora

BUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/

Wsignalorthebyteenables. Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupted data in the slave.

Functional Description

The IDT71321/IDT71421 provides two ports with separate control,

address and I/O pins that permit independent access for reads or writes

to any location in memory. The IDT71321/IDT71421 has an automatic

power down feature controlled by

CE. The CE controls on-chip power

down circuitry that permits the respective port to go into a standby mode

when not selected (

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(

(HEX), where a write is defined as the

II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen

flag (

(HEX) and to clear the interrupt flag (

memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,

sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

The

BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

the other side is completed. If a write operation has been attempted from

the side that receives a busy indication, the write signal is gated internally

to prevent the write from proceeding.

The use of

BUSYLogicisnotrequiredordesirableforallapplications.

In some cases it may be useful to logically OR the

BUSYoutputstogether

and use any

BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.Inslavemodethe

BUSYpinoperatessolely

as a write inhibit input pin. Normal operation can be programmed by tying

the

BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the

BUSY pin for that port LOW.

The

BUSY outputs on the IDT71321 (Master) are open drain type

outputs and require open drain resistors to operate. If these SRAMs are

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.

2691 drw 16

MASTER

Dual Port

SRAM

CE

MASTER

Dual Port

SRAM

CE

SLAVE

Dual Port

SRAM

CE

SLAVE

Dual Port

SRAM

CE

5V

5V

270

Ω

270

Ω

,