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UPSD323X 数据表(PDF) 38 Page - STMicroelectronics |
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UPSD323X 数据表(HTML) 38 Page - STMicroelectronics |
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38 / 176 page  µPSD323X 38/176 Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft) * indicates bit is not used and need to set to ’0.’ 21 Output Macrocells BC 22 Mask Macrocells AB 23 Mask Macrocells BC C0 Primary Flash Protection Sec7_ Prot Sec6_ Prot Sec5_ Prot Sec4_ Prot Sec3_ Prot Sec2_ Prot Sec1_ Prot Sec0_ Prot Bit = 1 sector is protected C2 Secondary Flash Protection Security _Bit ** * Sec3_ Prot Sec2_ Prot Sec1_ Prot Sec0_ Prot Security Bit = 1 device is secured B0 PMMR0 * * PLD Mcells clk PLD array- clk PLD Turbo * APD enable *00 Control PLD power consumption B4 PMMR2 * PLD array WRh PLD arrayAl e PLD array Cntl2 PLD array Cntl1 PLD array Cntl0 ** 00 Blocking inputs to PLD array E0 Page 00 Page Register E2 VM Periph- mode ** FL_da ta Boot_ data FL_co de Boot_c ode SR_co de Configure 8032 Program and Data Space CSIOP Addr Offset Register Name Bit Register Name Reset Value Comments 7 6 5 432 1 0 |
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