UPSD323X datasheet(39/176 Pages) STMICROELECTRONICS

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µPSD323X

INTERRUPT SYSTEM

There are interrupt requests from 10 sources as

follows.

INT0 external interrupt

2nd USART interrupt

Timer0 interrupt

I2C interrupt

INT1 external interrupt (or ADC interrupt)

DDC interrupt

Timer1 interrupt

USB interrupt

USART interrupt

Timer2 interrupt

External Int0

The INT0 can be either level-active or transition-

active depending on Bit IT0 in register TCON.

The flag that actually generates this interrupt is

Bit IE0 in TCON.

When an external interrupt is generated, the

corresponding request flag is cleared by the

hardware when the service routine is vectored

to only if the interrupt was transition activated.

If the interrupt was level activated then the

interrupt request flag remains set until the

requested interrupt is actually generated. Then

it has to deactivate the request before the

interrupt service routine is completed, or else

another interrupt will be generated.

Timer 0 and 1 Interrupts

Timer0 and Timer1 interrupts are generated by

TF0 and TF1 which are set by an overflow of

their respective Timer/Counter registers (except

for Timer0 in Mode 3).

These flags are cleared by the internal

hardware when the interrupt is serviced.

Timer 2 Interrupt

Timer2 interrupt is generated by TF2 which is

set by an overflow of Timer2. This flag has to be

cleared by the software - not by hardware.

It is also generated by the T2EX signal (timer 2

external interrupt P1.1) which is controlled by

EXEN2 and EXF2 Bits in the T2CON register.

This is the definition of Timer 2 as per 90C320

definition.

I2C Interrupt

The interrupt of the I

2C is generated by Bit INTR

in the register S2STA.

This flag is cleared by hardware.

External Int1

The INT1 can be either level active or transition

active depending on Bit IT1 in register TCON.

The flag that actually generates this interrupt is

Bit IE1 in TCON.

When an external interrupt is generated, the

corresponding request flag is cleared by the

hardware when the service routine is vectored

to only if the interrupt was transition activated.

If the interrupt was level activated then the

interrupt request flag remains set until the

requested interrupt is actually generated. Then

it has to deactivate the request before the

interrupt service routine is completed, or else

another interrupt will be generated.

The ADC can take over the External INT1 to

generate an interrupt on conversion being

completed

DDC Interrupt

The DDC interrupt is generated either by Bit

INTR in the S1STA register for DC2B protocol

or by Bit DDC interrupt in the DDCCON register

for DDC1 protocol or by Bit SWHINT Bit in the

DDCCON register when DDC protocol is

changed from DDC1 to DDC2.

Flags except the INTR have to be cleared by the

software. INTR flag is cleared by hardware.

USB Interrupt

The USB interrupt is generated when endpoint0

has transmitted a packet or received a packet,

when endpoint1 or endpoint2 has transmitted a

packet, when the suspend or resume state is

detected and every EOP received.

When the USB interrupt is generated, the

corresponding request flag must be cleared by

software. The interrupt service routine will have

to check the various USB registers to determine

the source and clear the corresponding flag.

Please see the dedicated interrupt control

registers for the USB peripheral for more

information.

UPSD323X 数据表(PDF) 39 Page - STMicroelectronics

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