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WM8756 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8756 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 39 page ![]() WM8756 Advance Information AI Rev 1.3 October 2001 9 DSD AUDIO MONOPHASE INTERFACE DSDCLK64 DSD[0:5] t DCL t DCH t DCY t DS t DH Figure 3 DSD Audio Data Timing – Normal Mode Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information DSDCLK64 cycle time tDCY 354.4 ns DSDCLK64 pulse width high tDCH 80 ns DSDCLK64 pulse width low tDCL 80 ns DSD[5:0] set-up time to DSDCLK64 rising edge tDS 10 ns DSD[5:0] hold time from DSDCLK64 rising edge tDH 10 ns Table 8 DSD Audio Data Timing – Normal Mode |
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