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WM8756 数据表(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8756 数据表(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 39 page  WM8756 Advance Information AI Rev 1.3 October 2001 30 1:0 FMT[1:0] 00 Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode LRCIN Polarity or LRCIN Phase 2LRP 0 Left Justified / Right Justified / I2S 0: Standard LRCIN Polarity 1: Inverted LRCIN Polarity DSP Mode 0: DSP early mode 1: DSP late mode 3 BCP 0 BCKIN Polarity 0: Normal (DIN[2:0] and LRCIN sampled on rising edge) 1: Inverted (DIN[2:0] and LRCIN sampled on falling edge) 5:4 IWL[1:0] 0 Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 0000011 Interface Control 8:6 REV[2:0] 000 Controls the output phase of the three stereo channels 1 in bit 6 reverses the phase of data output on OUT0L/R. 1 in bit 7 reverses the phase of data output on OUT1L/R. 1 in bit 8 reverses the phase of data output on OUT2L/R. 7:0 L1A[7:0] 11111111 (0dB) Attenuation level of left channel DACL1 in 0.5dB steps, see Table 15 Attenuation Control Levels. 0000100 Attenuation DACL1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. 7:0 R1A[7:0] 11111111 (0dB) Attenuation level of right channel DACR1 in 0.5dB steps, see Table 15 Attenuation Control Levels. 0000101 Attenuation DACR1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. 7:0 L2A[7:0] 11111111 (0dB) Attenuation level of left channel DACL2 in 0.5dB steps, see Table 15 Attenuation Control Levels. 0000110 Attenuation DACL2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. 7:0 R2A[7:0] 11111111 (0dB) Attenuation level of right channel DACR2 in 0.5dB steps, see Table 15 Attenuation Control Levels. 0000111 Attenuation DACR2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. 7:0 MASTA[7:0] 11111111 (0dB) Attenuation level of all channels in 0.5dB steps. See Table 15 Attenuation Control Levels 0001000 Master Attenuation (all channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store MASTA[7:0] and update attenuation on all channels. |
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