SP3T PIN Diode Switch

Rev. V1

MSW310x-310

8

8

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8

State 1

In State 1, the path from port J0 to J1 is in its low

insertion loss condition. The paths from port J0 to

port J2, and port J0 to port J3, are in their high

isolation states. In State 1, the control voltage

applied to CTL 1 is TTL-logic high, and the control

voltages applied to CTL 2 and CTL 3 are TTL-logic

low. CTL 1 logic forward biases the series PIN

diode between the J0 and J1 ports by applying 0 V

to the J1 bias input port (P1-J1), CTL2 & CTL 3 will

re-verse bias the series diodes connected from port

J0 to port J2, and from port J0 to port J3. The

magnitude of the resultant bias current through the

forward-biased diode is primarily determined by the

voltage applied to the J0 bias port (P1-J0)

(5 V nominal), the magnitude of the forward voltage

across the PIN diode and the resistance of R1.

This current is nominally 100 mA. At the same

time, the shunt PIN diodes connected between port

J2 and B2 and between port J3 and B3 are also

forward biased by applying a high bias voltage,

nominally 28 V, to the J2 and J3 bias ports (P1-J2,

P1-J3) and 0 V to the B2 and B3 bias ports (P1-B2,

P1-B3). The magnitudes of the bias currents

through these diodes are primarily determined by

the voltage applied to the J2 and J3 bias ports, the

magnitudes of the forward voltage across each of

the PIN diodes and the resistances of R4 and R5.

These currents are nominally 25 mA each. Under

this condition, the series PIN diodes connected

between the J0 and J2 ports, between the J0 and

J3 ports and the shunt diode between J1 and B1

are each reverse biased. The reverse bias voltage

applied to non-conducting diodes must be suffi-

ciently large to maintain each diode in its non- con-

ducting, high impedance state when a large RF

signal voltage may be present. For example, as-

sume a large RF signal is present in the J0- to-J1

path. The reverse

bias voltage across each of the series diodes in the

other paths is the arithmetic difference of the bias

voltage applied to the J2 bias port or J3 bias port

and the DC forward voltage of the forward-biased

J0-to-J1 series PIN diode. The minimum voltage

required to maintain the series diode between ports

J0 and J2 and the series diode between ports J0

and J3 out of conduction is a function of the magni-

tude of the RF voltage present, the standing wave

present at the se-ries diode’s anode, the frequency

of the RF signal and the characteristics of the se-

ries diode, among other factors. The minimum re-

verse bias voltage may be calculated as described

in the “Minimum Reverse Bias Voltage” section.

Truth Table

SP3T Switch Operation with PIN Diode Driver (MPDT3T28125-701) Interface

Path

J0 - J1

Path

J0 - J2

Bias:

J1

Bias:

J2

Bias:

J2

Bias:

B1

Path

J0 - J2

Bias:

B2

Bias:

B3

Bias:

J0

CTRL

1

CTRL

2

CTRL

3

RF

State

Low

Loss

High

Isolation

0 V,

-100 mA

+27 V,

0 mA

+27 V,

0 mA

+27 V,

0 mA

High

Isolation

0 V,

-25 mA

0 V,

-25 mA

+5 V,

+100 mA

1

High

Isolation

Low

Loss

+27 V,

0 mA

0 V,

-100 mA

+27 V,

0 mA

0 V,

-25 mA

High

Isolation

+27 V,

0 mA

0 V,

-25 mA

+5 V,

+100 mA

2

High

Isolation

High

Isolation

+27 V,

0 mA

+27 V,

0 mA

0 V,

-100 mA

0 V,

-25 mA

Low

Loss

0 V,

-25 mA

+27 V,

0 mA

+5 V,

+100 mA

3