SP3T PIN Diode Switch

Rev. V1

MSW310x-310

10

10

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10

State 2

In State 2, the path from port J0 to J2 is in its low

insertion loss condition. The path from port J0 to port

J1, and the path from port J0 to port J3, are in their

high isolation states. In State 2, the control voltage

applied to CTL 2 is TTL-logic high, and the control

voltages applied to CTL 1 and CTL 3 are TTL-logic

low, which forward biases the series PIN diode

between the J0 and J2 ports by applying 0 V to the

J2 bias input port (P1-J2), while reverse-biasing the

series diodes connected from port J0 to port J1, and

from port J0 to port J3. The magnitude of the resul-

tant bias current through the forward-biased diode is

primarily determined by the voltage applied to the J0

bias port (P1-J0) (5 V nominal), the magnitude of the

forward voltage across the PIN diode and the

resistance of R1. This current is nominally 100 mA.

At the same time, the shunt PIN diodes connected

between port J1 and B1 and between port J3 and B3

are also forward biased by applying a high bias

voltage, nominally 28 V, to the J1 and J3 bias ports

(P1-J1, P1-J3) and 0 V to the B1 and B3 bias ports

(P1-B2, P1-B3). The magnitudes of the bias currents

through these diodes are primarily determined by

the voltage applied to the J1 and J3 bias ports, the

magnitudes of the forward voltage across each of

the PIN diodes and the resistances of R2 and R5.

These currents are nominally 25 mA each. Under

this condition, the series PIN diodes connected

between the J0 and J1 ports, between the J0 and J3

ports and the shunt diode between J2 and B2 are

each reverse biased.

The reverse bias voltage applied to non-conducting

diodes must be sufficiently large to maintain each

diode in its non-conducting, high impedance state

when a large RF signal voltage may be present. For

example, assume a large RF signal is present in the

J0-to-J2 path. The reverse bias voltage across each

of the series diodes in the other paths is the

arithmetic difference of the bias voltage applied to

the J1 bias port or J3 bias port and the DC forward

voltage of the forward-biased J0-to-J2 series PIN

diode.

State 3

In State 3, the path from port J0 to J3 is in its low

insertion loss condition. The path from port J0 to port

J1, and the path from port J0 to port J2, is in their

high isolation states.

In State 3, the control voltage applied to CTL 3 is

TTL-logic high, and the control voltages applied to

CTL 1 and CTL 2 are TTL-logic low, which forward

biases the series PIN diode between the J0 and J3

ports by applying 0 V to the J3 bias input port (P1-

J3), while reverse-biasing the series diodes con-

nected from port J0 to port J1, and from port J0 to

port J2. The magnitude of the resultant bias current

through the forward-biased diode is primarily

determined by the voltage applied to the J0 bias port

(P1-J0) (5 V nominal), the magnitude of the forward

voltage across the PIN diode and the resistance of

R1. This current is nominally 100 mA.

At the same time, the shunt PIN diodes connected

between port J1 and B1 and between port J3 and B2

are also forward biased by applying a high bias

voltage, nominally 28 V, to the J1 and J2 bias ports

(P1-J1, P1-J2) and 0 V to the B1 and B2 bias ports

(P1-B2, P1-B2). The magnitudes of the bias currents

through these diodes are primarily determined by

the voltage applied to the J1 and J2 bias ports, the

magnitudes of the forward voltage across each of

the PIN diodes and the resistances of R2 and R4.

These currents are nominally 25 mA each. Under

this condition, the series PIN diodes connected be-

tween the J0 and J1 ports, between the J0 and J2

ports and the shunt diode between J3 and B3 are

each reverse biased.

The reverse bias voltage applied to non-conducting

diodes must be sufficiently large to maintain each

diode in its non-conducting, high impedance state

when a large RF signal voltage may be present. For

example, assume a large RF signal is present in the

J0-to-J3 path. The reverse bias voltage across each

of the series diodes in the other paths is the

arithmetic difference of the bias voltage applied to

the J1 bias port or J2 bias port and the DC forward

voltage of the forward-biased J0-to-J3 series PIN

diode.