Application Notes

THEORY OF OPERATION

The LP3944 takes incoming data and feed them into several

registers that control the frequency and the duty cycle of the

LEDs. Two prescaler registers and two PWM registers pro-

vide two individual rates to dim or blink the LEDs (for more

information on these registers, refer to Table 1. LP3944

REGISTER

TABLE).

The

baseband

controller/

microprocessor can program each LED to be in one of four

states — on, off, DIM0 rate or DIM1 rate. One read-only

registers provide status on all 8 LEDs. The LP3944 can be

used to drive RGB LEDs and/or single-color LEDs to create

a colorful, entertaining, and informative setting. This is par-

ticularly suitable for accessory functions in cellular phones

and toys. Any LED pins not used to drive LED can be used

for General Purpose Parallel Input/Output (GPIO) expan-

sion.

The LP3944 is equipped with Power-On Reset that holds the

chip in a reset state until V

Once V

initializes itself to the default state.

To bring the LP3944 into reset, hold the RST pin LOW for a

period of TW. This will put the chip to its default state. The

LP3944 can only be programmed after RST signal is HIGH

again.

I

The data on SDA line must be stable during the HIGH period

of the clock signal (SCL). In other words, state of the data

line can only be changed when CLK is LOW.

I

START and STOP bits classify the beginning and the end of

the I

transitioning from HIGH to LOW while SCL line is HIGH.

STOP condition is defined as the SDA transitioning from

LOW to HIGH while SCL is HIGH. The I

generates START and STOP bits. The I

to be busy after START condition and free after STOP con-

dition. During data transmission, I

repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long with

the most significant bit (MSB) being transferred first. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte of data has to be followed by an

acknowledge bit. The acknowledge related clock pulse is

generated by the master. The transmitter releases the SDA

line (HIGH) during the acknowledge clock pulse. The re-

ceiver must pull down the SDA line during the 9th clock

pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte

has been received.

After the START condition, a chip address is sent by the I

master. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). The LP3944 hardwires

bits 7 to 4 and leaves bits 3 to 1 selectable, as shown in

Figure 3. For the eighth bit, a “0” indicates a WRITE and a

“1” indicates a READ. The LP3944 supports only a WRITE

during chip addressing. The second byte selects the register

to which the data will be written. The third byte contains data

to write to the selected register.

20085306

FIGURE 1. I

20085307

FIGURE 2. I

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