PD243X, PD353X, PD443X

2006-01-23

7

DC Characteristics at 25°C

Parameter

Limits

Conditions

Min.

Typ.

Max.

Units

V

CC

4.5

5.0

5.5

Volts

Nominal

I

—

2.5

3.5

mA

V

I

PD243X

PD353X

PD443X

—

115

145

150

130

165

170

mA

mA

mA

V

V

V

V

IL

—

—

0.8

Volts

V

V

IH

2.0

—

—

Volts

V

I

(1)

25

—

100

µA

V

V

OL

—

—

0.4

Volts

V

V

OH

2.4

—

—

Volts

V

I

OH

–8.9

—

—

mA

V

I

OL

1.6

—

—

mA

V

Data I/O Bus Loading

—

—

100

pF

—

Clock I/O Bus Loading

—

—

240

pF

—

1)

D0 to D7 have no pull-up resistors so current is negligible.

Pin Assignments and Definitions

Pin

Function

Definition

Pin

Function

Definition

1

RD

Active low, will enable a processor to read all

registers in the display.

11

WR

Write. Active low. If the device is selected, a

low on the write input loads the data into mem-

ory.

2

CLK I/O

If CLK SEL (pin 3) is low, then expect an exter-

nal clock source into this pin. If CLK SEL is

high, then this pin will be the master or source

into this pin. If CLK SEL is high, then this pin

will be the master or source for all other

devices which have CLK SEL low.

12

D7

Data Bus bit 7 (MSB).

3

CLKSEL

CLOCK SELECT determines the action of pin

2. CLK I/O, see the section on Cascading for

an example.

13

D6

Data Bus bit 6.

4

RST

Reset. Used to synchronize blinking. Will not

clear the display. The reset pulse should be

less than 1 ms

14

D5

Data Bus bit 5.

5

CE1

Chip enable (active high).

15

D4

Data Bus bit 4.

6

CE0

Chip enable (active low).

16

D3

Data Bus bit 3.

7

A2

Address input (MSB).

17

D2

Data Bus bit 2.

8

A1

Address input.

18

D1

Data Bus bit 1.

9

A0

Address input (LSB).

19

D0

Data Bus bit 0 (LSB).

10

GND

Ground.

20

V

CC

Positive power pin.