PD243X, PD353X, PD443X

2006-01-23

12

Electrical and Mechanical Considerations

The CMOS IC of the display is designed to provide resistance to

both Electrostatic Discharge Damage and Latch Up due to voltage

or current surges. Several precautions are strongly recommended

to avoid overstressing these built-in safeguards.

ESD Protection

Display users should be careful to handle the devices consistent

with Standard ESD protection procedures. Operators should wear

appropriate wrist, ankle or feet ground straps and avoid clothing

that collects static charges. Work surfaces, tools and transport car-

riers that come into contact with unshielded devices or assemblies

should also be appropriately grounded.

Latch up Protection

Latch up is a condition that occurs in CMOS ICs after the input

protection diodes have been broken down. These diodes can be

reversed through several means:

V

on the inputs. When these situations exist, the IC may develop the

response of an SCR and begin conducting as much as one amp

through the V

until device failure or the device is turned off.

The Voltage Transient Suppression Techniques and buffer inter-

faces for longer cable runs help considerably to prevent latch con-

ditions from occurring. Additionally, the following Power Up and

Power Down sequence should be observed.

Power up Sequence

1. Float all active signals by tri-stating inputs to displays.

2. Apply V

3. Apply active signals to the displays by enabling all input

signals per application.

Power Down Sequence

1.Float all active signals by tri-stating the inputs to the display.

2.Turn off the power to the display.

Soldering Considerations

These displays can be hand soldered with SN63 solder using a

grounded iron set to 260°C.

Wave soldering is also possible following these conditions: Pre-

heat that does not exceed 93°C on the solder side of the PC board

or a package surface temperature of 85°C. Water soluble organic

acid flux (except carboxylic acid) or rosin-based RMA flux without

alcohol can be used.

Wave temperature is 245°C ±5°C with a dwell between 1.5 sec to

3.0 sec. Exposure to the wave should not exceed temperatures

above 260°C, for 5 sec at 1.59 mm (0.063") below the seating

plane. The packages should not be immersed in the wave.

Voltage Transient Suppression

It has become common practice to provide 0.01 µF bypass capac-

itors liberally in digital systems. Like other CMOS circuitry, the

Intelligent Display controller chip has very low power consumption

and the usual 0.01 µF would be adequate were it not for the

LEDs. To prevent power supply transients, capacitors with low

inductance and high capacitance at high frequencies are

required. This suggests a solid tantalum or ceramic disc for high

frequency bypass. For multiple display module systems distribute

the bypass capacitors evenly, keeping capacitors as close to the

power pins as possible. Use a 0.01 µF capacitor for each display

module and a 22 µF for every third display module.

Notes:

1. A2 must be held high for ASCII data.

2. Bit D7=1 enables attributes for the assigned digit.

Character Set

IDCS5087

ASCII

CODE

D0

D1

D2

D3

HEX

D4

D5

D6

000

0

1

1

0

0

2

01 0

3

01

1

4

10

0

5

10

1

6

11 0

7

111

0

0

0

0

0

1

0

0

1

0

2

0

0

0

1

3

0

0

1

1

4

0

1

0

0

5

0

1

1

0

6

0

1

0

1

7

0

1

1

1

8

1

0

0

0

9

1

0

1

0

A

1

0

0

1

B

1

0

1

1

C

1

1

0

0

D

1

1

1

0

E

1

1

0

1

F

1

1

1

1