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AD8250

Data Sheet

Rev. C | Page 16 of 24

Table 5. Truth Table Logic Levels for Transparent Gain Mode

Gain

−VS

Low

−VS

Low

High

−VS

High

Low

−VS

High

Latched Gain Mode

Some applications have multiple programmable devices such as

multiplexers or other programmable gain instrumentation

amplifiers on the same PCB. In such cases, devices can share a

data bus. The gain of the AD8250 can be set using WR as a latch,

allowing other devices to share A0 and A1. Figure 49 shows a

schematic using this method, known as latched gain mode. The

AD8250 is in this mode when WR is held at logic high or logic

low, typically 5 V and 0 V, respectively. The voltages on A0

and A1 are read on the downward edge of the WR signal as it

transitions from logic high to logic low. This latches in the logic

levels on A0 and A1, resulting in a gain change. See the truth

table in Table 6 for more information on these gain changes.

+15V

–15V

+IN

–IN

10μF0.1µF

DGND

REF

AD8250

+5V

G = PREVIOUS

STATE

G = 10

–

NOTE:

1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS

FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0

AND A1 ARE READ AND LATCHED IN, RESULTING IN A

GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.

Figure 49. Latched Gain Mode, G = 10

Table 6. Truth Table Logic Levels for Latched Gain Mode

Gain

High to low

Low

Change to 1

High to low

Low

High

Change to 2

High to low

High

Low

Change to 5

High to low

High

Change to 10

Low to low

No change

Low to high

No change

High to high

No change

1 X = don’t care.

On power-up, the AD8250 defaults to a gain of 1 when in latched

gain mode. In contrast, if the AD8250 is configured in transparent

gain mode, it starts at the gain indicated by the voltage levels on

A0 and A1 at power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 have to be held

for a minimum setup time, tSU, before the downward edge of

WR latches in the gain. Similarly, they must be held for a

minimum hold time of tHD after the downward edge of WR to

ensure that the gain is latched in correctly. After tHD, A0 and A1

can change logic levels, but the gain does not change (until the

next downward edge of WR). The minimum duration that WR

can be held high is t WR-HIGH, and the minimum duration that

WR can be held low is t WR-LOW. Digital timing specifications are

listed in Table 2. The time required for a gain change is dominated

by the settling time of the amplifier. A timing diagram is shown

in Figure 50.

When sharing a data bus with other devices, logic levels applied

to those devices can potentially feed through to the output of

the AD8250. Feedthrough can be minimized by decreasing the

edge rate of the logic signals. Furthermore, careful layout of the

PCB also reduces coupling between the digital and analog portions

of the board. Pull-up or pull-down resistors should be used to

provide a well-defined voltage at the A0 and A1 pins.

A0, A1

tSU

tHD

tWR-HIGH

tWR-LOW

Figure 50. Timing Diagram for Latched Gain Mode

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