P9235A-R Datasheet

© 2016 Integrated Device Technology, Inc

11

May 17, 2016

Applications Information

LDOs

There are three internal LDOs, which supply the P9235A-R internal voltage rails. Do not externally load any of the LDOs. VO_5 is the output

of a high voltage LDO, which serves as the pre-regulator. VO_5 initially supplies the input voltage to the other two LDOs until the buck

regulator output voltage powers up.

The other two LDOs, VO_33 and VO_18, have output voltages of 3.3 V and 1.8 V, respectively. The analog circuitry is power by the 3.3 V

LDO. The digital circuitry is powered by the 1.8 V LDO.

LDO Input and Output Capacitors

For proper load voltage regulation and operational stability, low ESR ceramic capacitors are required on the input and output of each LDO. A

10 µF low ESR ceramic cap is recommended for both the input (C19) and output (C14, C27, C29) capacitors. The capacitor’s connection to

the ground pin should be as short as possible for optimal device performance.

Buck Regulator

The buck regulator is the power supply for the 3.3 V and 1.8 V LDOs, and thus for all the internal analog and digital circuitry, excluding the

pre-regulator only. Do not externally load any of the LDOs. The current sourcing capability of this internal buck regulator is 50 mA maximum.

The two half bridge gate driver circuits are directly power by the buck regulator.

The P9235A-R buck regulator operates in hysteretic pulse mode to set the output voltage and will regulate the output voltage at 5 V (typical)

when VIN is greater than 5.5 VDC. For operation with VIN less than 5.5 V, the buck output will decrease below 5 V. When the VIN is less than

5 V, the regulator will switch to a linear mode that is similar to a LDO.

The input (C18, C19) and output (C20, C21) capacitors must be connected directly between each power rail pins and power GND pin (and

placed as close as possible to the respective IC pins). The output capacitors should be selected based on the typical reference schematic to

guarantee control loop stability. A 10 µF low ESR ceramic cap is recommended for both the bulk input (C19) and bulk output (C21) capacitor.

The buck regulator output voltage is connected to the VIN_LDO pin; therefore, the connection from the buck output to the VIN_LDO pin

should be made as wide and short as possible to minimize output voltage errors.

Buck Inductor Selection

A 4.7 µH inductor (L1) is used for the P9235A-R buck regulator. Select the inductor saturation current rating to exceed the value of peak

inductor current (during normal operation and start up). The inductor included in the Bill of Materials is recommended. Keep the inductor DCR

to a minimum to improve the efficiency of the regulator.

Decoupling Capacitors

As with any high-performance mixed-signal IC, P9235A-R must be isolated from the system power supply noise. A decoupling capacitor of

0.1 μF should be connected between each power supply pin (includes VIN, the buck regulator, LDOs, VBRG_IN, V_BRIDGE: C18, C20, C28,

C9, C12, C31) and the PCB ground plane. It must be placed as close as possible to these pins. The decoupling capacitor must be mounted

on the component side of the PCB.

Note: The VO_33 does not need this decoupling capacitor if the user follows the IDT recommended, optimized layout.

Full Bridge Input Capacitor

At least one 10 μF capacitor (C19) must be placed at the VIN pin. At least three 10 μF capacitors (C10, C11, C30) must be placed across the

full bridge voltage source (the V_BRIDGE node in the schematic) to minimize voltage ripple and voltage drop due to the large current

requirements. The full-bridge is used to convert DC voltage to AC voltage for power transfer. These 10 μF capacitors must be placed as close

as possible to the respective pins.

Note: If the half bridge FETs are not physically close together then two 10 μF capacitors per half bridge are needed. Follow the IDT optimized

layout in order to minimize these capacitors