LM81 datasheet(13/32 Pages) NSC

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Functional Description (Continued)

3.0 USING THE LM81

3.1 Power On

When power is first applied, the LM81 performs a “power on

reset” on several of its registers. The power on condition of

the LM81’s registers in shown in

Table 1 Registers whose

power on values are not shown have power on conditions

that are indeterminate (this includes the value RAM ,exclu-

sive of the DAC data, and WATCHDOG limits). When power

is first applied the ADC is inactive. In most applications, usu-

ally the first action after power on is usually to write WATCH-

DOG limits into the Value RAM. Register values can be re-

turned to their default values after power is applied to the

LM81 by taking RESET low for at least 50 ns.

3.2 Resets

Configuration Register INITIALIZATION accomplishes the

same function as power on reset on most registers. The

Value RAM conversion results, and Value RAM WATCH-

DOG limits are not Reset and will be indeterminate immedi-

ately after power on. If the Value RAM contains valid conver-

sion results and/or Value RAM WATCHDOG limits have

been previously set, they will not be affected by a Configura-

tion Register INITIALIZATION. Power on reset, or Configura-

tion Register INITIALIZATION, clear or initialize the following

registers (the initialized values are shown on

Table 1:

•

Configuration Register

•

Interrupt Status Register 1

•

Interrupt Status Register 2

•

INT Mask Register 1

•

INT Mask Register 2

•

VID/Fan Divisor Register

•

Serial Bus Address Register (Power on reset only, not re-

set by Configuration Register INITIALIZATION)

•

VID4 Register

•

Temperature Configuration Register

•

Extended Mode Register 1

•

Extended Mode Register 2

Configuration Register INITIALIZATION is accomplished by

setting Bit 7 of the Configuration Register high. This bit auto-

matically clears after being set.

3.3 Using the Configuration Register

The Configuration Register controls the LM81 operation. At

power on, the ADC is stopped and INT_Clear is asserted,

clearing the INT hardwire output. The Configuration Register

starts and stops the LM81, enables and disables interrupt

output, and provides the Reset function described in

Section

3.2.

Bit 0 of the Configuration Register controls the monitoring

loop of the LM81. Setting Bit 0 low stops the LM81 monitor-

ing loop and puts the LM81 in shutdown mode, reducing

power consumption. Serial Bus communication can take

place with any register in the LM81 although activity on the

SMBData and SMBCLK lines will increase shutdown current,

up to as much as maximum rated supply current, while the

activity takes place. Taking Bit 0 high starts the monitoring

loop, described in more detail subsequently.

Bit 1 of the Configuration Register enables the INT Interrupt

hardwire output when this bit is taken high.

Bit 3 of the Configuration Register clears the INT output

when set high, without affecting the contents of the Interrupt

Status Registers. The LM81 will stop monitoring. It will re-

sume upon clearing of this bit.

Bit 4 of the Configuration Register provides an active low 20

ms pulse at the RESET output when set high.

The CI_Clear provides an active low 20 ms pulse at the CI

output pin when set high. This is intended for resetting the

Chassis Intrusion circuitry.

The INITIALIZATION bit resets the internal registers of the

LM81 as described in

Section 3.2.

3.4 Starting Conversions

The monitoring function (Analog inputs, temperature, and

fan speeds) in the LM81 is started by writing to the Configu-

ration Register and setting INT_Clear (Bit 3), low, and Start

(bit 0), high. The LM81 then performs a “round-robin” moni-

toring of all analog inputs, temperature, and fan speed inputs

approximately once every 400 ms. The sequence of items

being monitored corresponds to locations in the Value RAM

and is:

Temperature

Vccp2

+12Vin

+5Vin

+3.3Vin

Vccp1

+2.5Vin

Fan 1

Fan 2

DACOut immediately changes after the DAC Data Register

in the Value RAM has been updated. For a zero to full scale

transition DACOut will typically settle within 100 µsec of the

stop by master in the write to the DAC Data Register Serial

Bus transaction. The DAC Data Register is not reset by the

INITIALIZATION bit found in the Configuration Register.

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