ZSC31150 Datasheet

© 2016 Integrated Device Technology, Inc.

15

December 6, 2016

2.4 Temperature Measurement

The ZSC31150 supports four different methods for acquiring the temperature data needed for calibration of the sensor signal in the specified

temperature range.

Temperature data can be acquired using one of these temperature sensors:



an internal pn-junction temperature sensor





an external resistive half bridge temperature sensor



the temperature coefficient of the sensor bridge at bridge current excitation

Refer to the ZSC31150 Functional Description for a detailed explanation of temperature sensor adaptation and adjustment.

2.5 System Control and Conditioning Calculation

The system control supports the following tasks/features:



Controlling the measurement cycle according to the EEPROM-stored configuration data



Performing the16-bit correction calculation for each measurement signal using the EEPROM-stored calibration coefficients and ROM-

based algorithms; i.e., the signal conditioning



Managing the start-up sequence and starting signal conditioning



Handling communication requests received by the digital interface



Managing failsafe tasks for the functions of the ZSC31150 and indicating detected errors with diagnostic states

Refer to the ZSC31150 Functional Description for a detailed description.

2.5.1 Operation Modes

The internal state machine has three main states:



The continuously running signal conditioning mode, which is called Normal Operation Mode (NOM)



The calibration mode with access to all internal registers and states, which is called Command Mode (CM)



The failure messaging mode, which is called Diagnostic Mode (DM)

2.5.2 Start Up Phase

1. Internal supply voltage settling phase (i.e., the VDDA - VSSA potential), which is ended when the reset signal is disabled through

the power-on clear block (POR). Refer to the ZSC31150 Technical Note – High Voltage Protection document, section 4 for power

on/off thresholds.

Time (from beginning with VDDA-VSSA=0V): 500µs to 2000µs; AOUT is in tri-state

2. System start, EEPROM read out, and signature check (and ROM check if selected by setting EEPROM bit CFGAPP:CHKROM=1).

Time: ~200µs (~9000µs with ROM-check; i.e., 28180 clocks); AOUT is LOW (DM)

3. Processing the start routine for signal conditioning (all measurements and conditioning calculations).

Time: 5 x A/D conversion time; AOUT behavior depends on selected OWI mode (refer to section 2.6):



OWIANA & OWIDIS => AOUT is LOW (DM)



OWIWIN & OWIENA => AOUT is in tri-state