ZSC31015EAG1-R datasheet(20/52 Pages) IDT

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November 14, 2016

ZSC31015 Datasheet

2.5.

Clock Generator / Power-On Reset (CLKPOR)

If the power supply exceeds 2.5V (maximum), the reset signal de-asserts and the clock generator starts working

at a frequency of approximately 512kHz (±20%). The exact value only influences the conversion cycle time and

communication to the outside world but not the accuracy of signal processing. In addition, to minimize the

oscillator error as the VDD voltage changes, an on-chip regulator is used to supply the oscillator block.

2.5.1.

Trimming the Oscillator

Settings for the Osc_Trim bits in EEPROM fine-tune the oscillator frequency. See Table 3.5 for bit locations and

Table 2.2 for possible settings. The default value is 0HEX to ensure communication on start-up.

Important: Optimal oscillator trimming is determined during wafer-level testing and final package testing, and this

part-specific factory value, which can be copied to Osc_Trim, is stored in bits in the CUST_ID1 and CUST_ID2

EEPROM bits for applications requiring optimal response time. In this case, see section 5 for important notes and

instructions for copying these optimal values to the Osc_Trim bits before calibration. It is strongly recommended

that only the default value or the factory trim value be used because ZACwire

TM communication is not guaranteed

at different oscillator frequencies.

Table 2.2

Oscillator Trimming

Osc_Trim Bits

Delta Frequency (kHz)

100

+385

101

+235

110

+140

111

+65

000

Nominal

001

-40

010

-76

011

-110

Example: Programming 011B  the trimmed frequency = nominal value – 110 kHz.

2.6. Diagnostic Features

The ZSC31015 offers a full suite of di

agnostic features to ensure robust system operation in the most “mission-

critical” applications. If the part is programmed in Analog Output Mode, then diagnostic states are indicated by

an output below 2.5% of VDD or above 97.5% of VDD. If the part is programmed in Digital Output Mode, then

diagnostic states will be indicated by a transmission with a generated parity error.

Table 2.3 gives a summary of the diagnostic features, which are explained in detail in the following sections.

EEPROM settings that control diagnostic functions are given in section 3.5.

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