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ZSC31015EAG1-R 数据表(PDF) 43 Page - Integrated Device Technology |
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ZSC31015EAG1-R 数据表(HTML) 43 Page - Integrated Device Technology |
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43 / 52 page ![]() © 2016 Integrated Device Technology, Inc 43 November 14, 2016 ZSC31015 Datasheet 2 1 5 6 7 8 3 4 ZSC31015 Bsink VBP ExtTemp VBN VSS Sig TM VDD Vgate 0.1 F Vsupply Ground +5.5 to +30 V OUT Optional Bsink S D BSS169 4.2. Absolute Analog Voltage Output The figure below shows an application circuit for an absolute voltage output configuration with temperature com- pensation via internal temperature PTAT and external JFET regulation for all industry standard applications. Figure 4.2 Absolute Analog Voltage Output – Temperature Compensation via Internal Temperature PTAT with External JFET Regulation The output signal range can be one of the following options: 0 to 1 V analog output. The absolute voltage output reference is trimmable: 1 V (+/-3 mV) in the 1 V Output Mode via a 4-bit EEPROM field (see section 2.4.3). Rail-to-rail analog output. The on-chip reference for the JFET regulator block is trimmable: 5 V (±15 mV) in the Ratiometric Output Mode via a 4-bit EEPROM field. (See section 2.4.3). |
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