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WM8198SCDS/R 数据表(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8198SCDS/R 数据表(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 31 page ![]() WM8198 Production Data w PD Rev 4.0 June 2004 14 MCLK VSMP VS R S/CL (CDSREF = 00) R S/CL (CDSREF = 01) R S/CL (CDSREF = 10) R S/CL (CDSREF = 11) Figure 8 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode; non-CDS processing is achieved by setting switch 2 in the lower position, CDS = 0. OFFSET ADJUST AND PROGRAMMABLE GAIN The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by a Programmable Gain Amplifier. The 9-bit PGA can operate in two modes, a wide gain range (linear on a dB scale) mode or a high resolution (linear in V/V) mode. The PGA mode is selected by setting the register bit PGAMODE. The default setting is PGAMODE=0 which selects the wide gain range mode. Figure 9 and Figure 10 show the transfer functions of the PGA in each mode. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[8:0]. Figure 9 Wide Range Gain Mode (PGAMODE=0) Figure 10 High-Res Gain Mode (PGAMODE=1) In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME, ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details. ADC INPUT BLACK LEVEL ADJUST The output from the PGA should be offset to match the full-scale range of the ADC (3V). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 128 256 384 512 Gain register code (PGA[8:0]) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 128 256 384 512 Gain Register Code (PGA[8:0]) |
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