WM8198

Production Data

w

PD Rev 4.0 June 2004

16

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

=

∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain. The PGA transfer characteristic varies with the value

of the PGAMODE register bit.

If PGAMODE = 0 (wide gain range PGA mode - default):

=

∗ 416/(566 - PGA[8:0]) ………................................... Eqn. 5a

If PGAMODE = 1 (high resolution PGA mode):

=

∗ (1 + PGA[8:0]x4/511).............................................. Eqn. 5b

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

∗ 65535} + 32767......... PGAFS[1:0] = 00 or 01 Eqn. 6

∗ 65535} ............................... PGAFS[1:0] = 11 Eqn. 7

∗ 65535} + 65535.................. PGAFS[1:0] = 10 Eqn. 8

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

OUTPUT FORMATS

The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by

setting control bit MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable

by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing

Diagrams section.

Figure 12 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 13 shows the output data

formats for Mode 3. Table 1 summarises the output data obtained for each format.

MCLK

4+4+4+4-BIT

OUTPUT

AB

AB

CD

8+8-BIT

OUTPUT

MCLK

4+4+4+4-BIT

OUTPUT

AB

8+8-BIT

OUTPUT

AB

C D

AB

Figure 12 Output Data Formats

(Modes 1

−−−− 2, 4 −−−− 6)

Figure 13 Output Data Formats

(Mode 3)