WM8753LEBSLASHV datasheet(14/87 Pages) WOLFSON

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Advanced Information

WM8753L

AI Rev 3.1 June 2004

Test Conditions

DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25

oC, Slave Mode

fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MODE/GPIO3 and CSB/GPIO5 to AVDD

and DCVDD power-up setup time

tpusetup

100

AVDD and DCVDD to MODE/GPIO3 and

CSB/GPIO5 hold time

tpuhold

DBVDD powerup to DCVDD or AVDD

powerup

tdbpu

Note:

DBVDD must be supplied before or at same time as either DCVDD or AVDD to ensure MODE and CSB are defined

internally when power on reset is released

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25

oC,

Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRC / VXFS propagation delay from BCLK / VXCLK falling

edge

tDL

ADCDAT / VXDOUT propagation delay from BCLK / VXCLK

falling edge

tDDA

DACDAT / VXDIN setup time to BCLK / VXCLK rising edge

tDST

DACDAT / VXDIN hold time from BCLK / VXCLK rising edge

tDHT

WM8753LEB/V 数据表(PDF) 14 Page - Wolfson Microelectronics plc

WM8753LEB/V 数据表(HTML) 14 Page - Wolfson Microelectronics plc

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