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WM8955 数据表(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8955 数据表(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 43 page  Product Preview WM8955L w Product Preview Rev 0.4 May2003 13 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DBVDD = 3.3V, DGND = 0V, TA =+25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 0 400 kHz SCLK Low Pulse-Width t1 600 ns SCLK High Pulse-Width t2 1.3 us Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDIN, SCLK Rise Time t6 300 ns SDIN, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed tps 05 ns |
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