Application Notes

BLOCK DIAGRAM AND OPEATIONAL DESCRIPTION

A) INPUT STAGE:

As can be seen from the simplified schematic in Figure 1, the

input stage consists of two distinct differential pairs (Q1-Q2

and Q3-Q4) in order to accommodate the full Rail-to-Rail

input common mode voltage range. The voltage drop across

R5, R6, R7 and R8 is kept to less than 200mV in order to

allow the input to exceed the supply rails. Q13 acts as a

switch to steer current away from Q3-Q4 and into Q1-Q2, as

the input increases beyond 1.4 of V

signal path from the bottom stage differential pair to the top

one and causes a subsequent increase in the supply current.

In transitioning from one stage to another, certain input stage

parameters (V

on which differential pair is “on” at the time. Input Bias

current, I

crosses the transition region. In addition, parameter such as

PSRR and CMRR which involve the input offset voltage will

also be effected by changes in V

pair transition region.

The input stage is protected with the combination of R9-R10

and D1, D2, D3 and D4 against differential input over-

voltages. This fault condition could otherwise harm the dif-

ferential pairs or cause offset voltage shift in case of pro-

longed over voltage. As shown in Figure 2, if this voltage

and current flow is limited by the internal series resistors (R9

tial on V

variation, the point were the diodes turn on will change at the

rate of 5mV/˚C

B) OUTPUT STAGE:

The output stage (see Figure 1) is comprised of complimen-

tary NPN and PNP common-emitter stages to permit voltage

swing to within a V

sourcing and Q10 supplies the sinking current load. Output

current limiting is achieved by limiting the V

using this approach to current limiting, alleviates the draw

back to the conventional scheme which requires one V

be

reduction in output swing.

The frequency compensation circuit includes Miller capaci-

tors from collector to base of each output transistor (see

Figure 1,C

high frequency gain of the output transistors is high, and the

Miller effect increases the effective value of the capacitors

thereby stabilizing the Op Amp. Large capacitive loads

greatly decrease the high frequency gain of the output tran-

sistors thus lowering the effective internal Miller capacitance

- the internal pole frequency increases at the same time a

low frequency pole is created at the Op Amp output due to

the large load capacitor. In this fashion, the internal dominant

pole compensation, which works by reducing the loop gain to

less than 0dB when the phase shift around the feedback

loop is more than 180˚, varies with the amount of capacitive

load and becomes less dominant when the load capacitor

has increased enough. Hence the Op Amp is very stable

even at high values of load capacitance resulting in the

uncharacteristic feature of stability under all capacitive loads.

C) OUTPUT VOLTAGE SWING CLOSE TO V

The LM8272’s output stage design allows voltage swings to

within millivolts of either supply rail for maximum flexibility

and improved useful range. Because of this design architec-

ture, as can be seen from Figure 1 diagram, with Output

approaching either supply rail, either Q9 or Q10 Collector-

Base junction reverse bias will decrease. With output less

than a V

tor operates near saturation. In this mode of operation, the

transistor will exhibit higher junction capacitance and lower f

t

which will reduce Phase Margin. With the Noise Gain (NG =

1 + Rf/Rg, Rf & Rg are external gain setting resistors) of 2 or

higher, there is sufficient Phase Margin that this reduction (in

Phase Margin) is of no consequence. However, with lower

10130870

FIGURE 1. Simplified Schematic Diagram

101308A4

FIGURE 2. Input Stage Current vs. Differential Input

Voltage

www.national.com

11