3

Integrated

Circuit

Systems, Inc.

ICS952601

0701G—10/13/04

Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

29

3V66_4/VCH

OUT

66.66MHz clock output for AGP support. AGP-PCI should be aligned

with a skew window tolerance of 500ps.

VCH is 48MHz clock output for video controller hub.

30

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

31

48MHz_USB

OUT

48MHz clock output.

32

48MHz_DOT

OUT

48MHz clock output.

33

GND

PWR

Ground pin.

34

VDD48

PWR

Power pin for the 48MHz output.3.3V

35

Vtt_PWRGD#

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine

when latch inputs are valid and are ready to be sampled. This is an

active low input.

36

VDD

PWR

Power supply for SRC clocks, nominal 3.3V

37

SRCCLKC

OUT

Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

38

SRCCLKT

OUT

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

39

GND

PWR

Ground pin.

40

CPUCLKC0

OUT

Complimentary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

41

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

42

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

43

CPUCLKC1

OUT

Complimentary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

44

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

45

GND

PWR

Ground pin.

46

CPUCLKC2

OUT

Complimentary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

47

CPUCLKT2

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

48

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

49

PCI_STOP#

IN

Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic

0 level, when input low. PCI and SRC clocks can be set to

Free_Running through I2C. Internal pull-up of 150K nominal.

50

CPU_STOP#

IN

Stops all CPUCLK besides the free running clocks. Internal pull-up of

150K nominal

51

FS_A

IN

Frequency select pin, see Frequency table for functionality

52

IREF

OUT

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

53

GND

PWR

Ground pin.

54

GNDA

PWR

Ground pin for core.

55

VDDA

PWR

3.3V power for the PLL core.

56

FS_B

IN

Frequency select pin, see Frequency table for functionality