ICS952601 datasheet(5/24 Pages) ICST

5 / 24 page

Integrated

Circuit

Systems, Inc.

ICS952601

0701G—10/13/04

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

VDD + 0.5V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5

VDD + 0.5V

Storage Temperature

-65

150

°C

Tambient

Ambient Operating Temp

070

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection human body model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

VIH

3.3 V +/-5%

VDD + 0.3

Input MID Voltage

VMID

3.3 V +/-5%

1.8

Input Low Voltage

VIL

3.3 V +/-5%

VSS - 0.3

0.8

Input High Current

IIH

VIN = VDD

-5

IIL1

VIN = 0 V; Inputs with no pull-up

resistors

-5

IIL2

VIN = 0 V; Inputs with pull-up

resistors

-200

Operating Supply Current

IDD3.3OP

Full Active, CL = Full load;

258

350

all diff pairs driven

all differential pairs tri-stated

0.3

Input Frequency

VDD = 3.3 V

14.31818

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs

COUT

Output pin capacitance

CINX

X1 & X2 pins

Clk Stabilization

1,2

TSTAB

From VDD Power-Up or de-

assertion of PD# to 1st clock

1.8

1,2

Modulation Frequency

Triangular Modulation

kHz

Tdrive_SRC

SRC output enable after

PCI_Stop# de-assertion

Tdrive_PD#

CPU output enable after

PD# de-assertion

300

Tfall_Pd#

PD# fall time of

Trise_Pd#

PD# rise time of

Tdrive_CPU_Stop#

CPU output enable after

CPU_Stop# de-assertion

Tfall_CPU_Stop#

PD# fall time of

Trise_CPU_Stop#

PD# rise time of

SMBus Voltage

VDD

2.7

5.5

Low-level Output Voltage

VOL

@ IPULLUP

0.4

Current sinking at VOL = 0.4 V

IPULLUP

4mA

SCLK/SDATA

Clock/Data Rise Time

TRI2C

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min VIH + 0.15) to (Max VIL - 0.15)

300

1Guaranteed by design, not 100% tested in production.

2See timing diagrams for timing requirements.

IDD3.3PD

3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet

ppm frequency accuracy on PLL outputs.

Input Capacitance

Input Low Current

Powerdown Current

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