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CS7410 数据表(PDF) 30 Page - Cirrus Logic |
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CS7410 数据表(HTML) 30 Page - Cirrus Logic |
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30 / 39 page ![]() CS7410 30 DS553PP1 1. Optional pull up or pull down resistor may be connected to configure internal ROM program 2. Required external resistor required to select processor boot from internal ROM (pull down) or external ROM (pull up). 3. Drives for a short time after reset, then reverts to high impedance 4.2 Miscellaneous Pins These pins described in Table8 are used for used for basic functions such as clocking, reset and infrared receiver interface. The main system clock can be derived from an external crystal connected between the XTLCLK_I and XTLCLK_O pins, or can be received from the CD servo chip via the XTLCLK_I pin. The CS7410 can accommodate a variety of input frequencies, such as 44.1 KHz x 256, x 384, or x 512. 4.3 Serial Interface Pins The CS7410 Serial Interface pins are described in Table9. CS7410 has three dedicated serial ports, each with different protocols. The 2-wire serial port (SER1) supports industry standard protocols. This port is typ- ically used for debug, with the CS7410 as the slave. The slave chip select address is programmable, and defaults to a 7-bit value of 0x1B. A second serial controller (SER2) supports industry standard 3-wire and 4-wire protocols. In master mode, this interface can control a front panel or a small non-volatile memory. In slave mode, it can operate under control of an external processor, for example, in a combination unit. The third serial port (SER3) is a 5-wire master device optimized for reading CD subcodes from the servo chip, and can also be used a general-purpose serial port. 98 GPIO_1 B4 I GPIO[1] B PWM_Out O 99 GPIO_2 B4 I GPIO[2] B 100 GPIO_3 B4 I GPIO[3] B Pin Name Type Reset Function #1 Dir Function #2 Dir Note Table 7. Pin Assignments (Continued) Pin Signal Name Type Description 17 XTLCLK_O O Crystal output 18 XTLCLK_I I Crystal input, or oscillator input 90 RST_N I Asynchronous reset input, active low 91 TEST I Manufacturing test, tie to ground Table 8. Miscellaneous Interface Pins Pin Signal Name Type Description 60 SER1_CLK B Debug port serial clock 61 SER1_DAT B Debug port serial data 65 SER2_CLK B Clock for 4-wire serial port (output for master mode, input for slave mode) 66 SER2_DI I Input data for 4-wire serial port 67 SER2_DO B Output data for 4-wire serial port – may function as bidi- rectional data in 3-wire mode. Table 9. Serial Interface Pins |
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