APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739

2

ABSOLUTE MAXIMUM RATINGS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

MOTOR VOLTAGE SUPPLY, HV

200V

OUTPUT CURRENT, peak

10A

5A

GATE SUPPLY VOLTAGE, Vcc

20V

LOGIC SUPPLY VOLTAGE, Vdd

20V

40W

LOGIC INPUT VOLTAGE

2.1°C/Watt

TEMPERATURE, pin solder, 10s

300°C

150°C

TEMPERATURE RANGE, storage

–55 to +150°C

OPERATING TEMPERATURE, case

–25 to +85°C

EB03

SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

POSITIVE OUTPUT VOLTAGE

198.1

201.9

Volts

HV=100V, Fpwm=50kHz, L=100 µH

NEGATIVE OUTPUT VOLTAGE

"

-1.7

1.9

Volts

POSITIVE EDGE DELAY

"

310

n-second

RISETIME

"

50

n-second

NEGATIVE EDGE DELAY

"

290

n-second

FALLTIME

"

50

n-second

PWM FREQUENCY

Set by external circuitry

50

kHz

INPUT IMPEDANCE

Set by internal resistors

50

k-ohm

INPUT

A logic level input independently controls each FET in

the half bridge. A logic level high turns on the FET and

low turns it off. A common shut down input turns off all

FETs when high.

All inputs are Schmitt triggers with the upper threshold at

interfaces with CMOS or HCMOS provided that the Vdd for

the logic family and the EB03 are the same.

TTL families may be used if a pull-up to Vcc is added to

the TTL gates driving the EB03, and Vdd for the EB03 is the

An open signal connector pulls the shut down input high

and all other inputs low, insuring that all outputs are off.

However, input impedance is 50k on all inputs; therefore if

one input is open circuited a high radiated noise level could

spuriously turn on a FET.

OUTPUT

Each output section consists of a switching mode FET half

bridge. Separate HV supply, emitter, and HV return lines are

provided for each section.

The FETs are conservatively rated to carry 5A. At 5A the

saturation voltage is 1.9V maximum.

Each FET has an intrinsic diode connected in anti-parallel.

When switching an inductive load this diode will conduct, and

the drop at 5A will be 1.9V maximum.

INPUT AND OUTPUT SIGNALS

NOTES: 1.

Over Entire Environmental Range.

2.

Long term operation at the maximum junction temperature will result in reduced product life. Lower internal temperature by

reducing internal dissipation or using better heatsinking to achieve high MTTF.

3.

Each FET.

PIN

SYMBOL

FUNCTION

PIN

SYMBOL

FUNCTION

1

Gate supply 3

13

HV1

High Voltage supply 1

2

Lin3

Low drive logic in 3

14

OUT1

Section 1 output

3

Hin3

High drive logic in 3

15

S1

Section 1 source

4

Logic supply

16

HVRTN1

Section 1 return

5

Gate supply 2

17

HV2

High voltage supply 2

6

Lin2

Low drive logic in 2

18

OUT 2

Section 2 output

7

Signal ground

19

S2

Section 2 source

8

Hin2

High drive logic in 2

20

HVRTN2

Section 2 return

9

Gate supply 1

21

HV3

High voltage supply 3

10

Lin1

Low drive logic in 1

22

OUT 3

Section 3 output

11

SD

Shut down logic in

23

S3

Section 3 source

12

Hin1

High drive logic in 1

24

HVRTN 3

Section 3 return