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STK17TA8-R45 数据表(PDF) 4 Page - List of Unclassifed Manufacturers

部件名 STK17TA8-R45
功能描述  nvTime??Event Data Recorder 128K x 8 AutoStore??nvSRAM with Real-Time Clock Product Preview
PDF  22 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

STK17TA8-R45 数据表(HTML) 4 Page - List of Unclassifed Manufacturers

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STK17TA8
February 2004
4
Document Control # ML0023 rev 0.3
SRAM READ CYCLES #1 & #2
(VCC = 3.0V +20%, -10%)e
Note g: W must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i:
Measured
± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
SRAM READ CYCLE #2: E Controlledg
NO.
SYMBOLS
PARAMETER
STK17TA8-25
STK17TA8-35
STK17TA8-45
UNITS
#1, #2
Alt.
MINMAX
MINMAX
MINMAX
1tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2tAVAVg
tRC
Read Cycle Time
25
35
45
ns
3tAVQVh
tAA
Address Access Time
25
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
10
15
20
ns
5tAXQXh
tOH
Output Hold after Address Change
3
3
3
ns
6tELQX
tLZ
Chip Enable to Output Active
3
3
3
ns
7tEHQZi
tHZ
Chip Disable to Output Inactive
10
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9tGHQZi
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICCHf
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCLf
tPS
Chip Disable to Power Standby
25
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
10
tELICCH
11
tEHICCL
7
tEHQZ
8
tGLQX
1
tELQV
9
tGHQZ



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