STK17TA8

February 2004

5

Document Control # ML0023 rev 0.3

SRAM WRITE CYCLES #1 & #2

Note j:

If W is low when E goes low, the outputs remain in the high-impedance state.

Note k: E or W must be

Note l:

HSB must be high during SRAM write cycles.

SRAM WRITE CYCLE #1: W Controlledk, l

SRAM WRITE CYCLE #2: E Controlledk, l

NO.

SYMBOLS

PARAMETER

STK17TA8-25

STK17TA8-35

STK17TA8-45

UNITS

#1

#2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

12

Write Cycle Time

25

35

45

ns

13

Write Pulse Width

20

25

30

ns

14

Chip Enable to End of Write

20

25

30

ns

15

Data Set-up to End of Write

10

12

15

ns

16

Data Hold after End of Write

0

0

0

ns

17

Address Set-up to End of Write

20

25

30

ns

18

Address Set-up to Start of Write

0

0

0

ns

19

Address Hold after End of Write

0

0

0

ns

20

Write Enable to Output Disable

10

13

15

ns

21

Output Active after End of Write

3

3

3

ns

PREVIOUS DATA

DATA OUT

E

ADDRESS

12

W

16

DATA IN

19

13

18

17

DATA VALID

20

15

HIGH IMPEDANCE

21

14

DATA IN

12

16

13

19

18

17

DATA VALID

15

HIGH IMPEDANCE

14

DATA OUT

E

ADDRESS

W

DATA IN