STK17TA8

February 2004

2

Document Control # ML0023 rev 0.3

PACKAGES

PIN DESCRIPTIONS

Pin Name

I/O

Description

Input

Address: The 17 address inputs select one of 131,072 bytes in the

nvSRAM array or one of 16 bytes in the clock register map.

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and

clock.

E

Input

Chip Enable: The active low E input selects the device.

W

Input

Write Enable: The active low W enables data on the DQ pins to be

written to the adddress location latched by the falling edge of E.

G

Input

Output Enable: The active low G input enables the data output buffers

during read cycles. Deasserting G high causes the DQ pins to tri-state.

Input

Crystal: Connections for 32.768 kHz crystal.

Power Supply

Capacitor supplied backup RTC supply voltage.

Power Supply

Battery supplied backup RTC supply voltage.

Power Supply

Power (+ 3V)

HSB

I/O

Hardware Store Busy (I/O)

INT

Output

Interrupt Output: Can be programmed to respond to the clock alarm,

the watchdog timer and the power monitor. Programmable to either

active high (push/pull) or active low (open-drain).

Power Supply

Autostore Capacitor: Supplies power to nvSRAM during power loss to

store data from SRAM to nonvolatile elements.

Power Supply

Ground

48 Pin 300 mil SSOP

40 Pin 600 mil DIP

(not to scale)