STK17TA8

February 2004

20

Document Control # ML0023 rev 0.3

M

Match. Setting this bit to 0 causes the seconds value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore

the seconds value.

1FFF1h

Timekeeping - Centuries

D7

D6

D5

D4

D3

D2

D1

D0

X

X

10s Centuries

Centuries

1FFF0h

Flags

D7

D6

D5

D4

D3

D2

D1

D0

WDF

AF

PF

X

X

CAL

W

R

WDF

Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is

cleared to 0 when the Flags/Control register is read.

AF

Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is

cleared when the Flags/Control register is read.

PF

Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold Vswitch. It is cleared to 0 when the Flags/Con-

trol register is read.

CAL

Calibration Mode. When set to 1, the clock enters calibration mode. When set to 0, the clock operates normally.

W

Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write them with updated values. Setting

the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters.

R

Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register. The user can

then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture,

so the bit must be returned to 0 prior to reading again.

1FFF2h

Alarm - Seconds

D7

D6

D5

D4

D3

D2

D1

D0