WM8772 datasheet(26/70 Pages) WOLFSON

26 / 70 page

WM8772EDS – 28 PIN SSOP

Production Data

PD Rev 4.1 October 2004

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

BCLK following a low to high LRC transition and may be sampled on the rising edge of BCLK. The

right channel ADC data is contiguous with the left channel data (Figure 27)

ADCLRC

ADCBCLK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCLK

Figure 27 DSP Early Mode Timing Diagram – ADC Data Output

DSP LATE MODE

In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the first

BCLK rising edge following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data

follow DAC channel 1 left data (Figure 28).

DACLRC

DACBCLK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 3

RIGHT

NO VALID DATA

Figure 28 DSP Late Mode Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

BCLK as the low to high LRC transition and may be sampled on the rising edge of BCLK. The right

channel ADC data is contiguous with the left channel data (Figure 29).

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 29 DSP Late Mode Timing Diagram – ADC Data Output

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