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LMF100CIWM 数据表(PDF) 2 Page - National Semiconductor (TI) |
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LMF100CIWM 数据表(HTML) 2 Page - National Semiconductor (TI) |
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2 / 28 page  Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Note 14) Supply Voltage (V + −V−) 16V Voltage at Any Pin V + + 0.3V V − − 0.3V Input Current at Any Pin (Note 2) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) 500 mW Storage Temperature 150˚C ESD Susceptability (Note 11) 2000V Soldering Information N Package: 10 sec. 260˚C J Package: 10 sec. 300˚C SO Package: Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. Operating Ratings (Note 1) Temperature Range T MIN ≤ TA ≤ TMAX LMF100CCN 0˚C ≤ T A ≤ +70˚C LMF100CIWM −40˚C ≤ T A ≤ +85˚C Supply Voltage 4V ≤ V+ −V− ≤ 15V Electrical Characteristics The following specifications apply for Mode 1, Q = 10 (R 1 = R3 = 100k, R2 = 10k), V + = +5V and V− = −5V unless otherwise specified. Boldface limits apply for T MIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions LMF100CCN LMF100CIWM Units Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Is Maximum Supply Current fCLK = 250 kHz 9 13 13 9 13 mA No Input Signal f0 Center Frequency MIN 0.1 0.1 Hz Range MAX 100 100 kHz fCLK Clock Frequency MIN 5.0 5.0 Hz Range MAX 3.5 3.5 MHz fCLK/f0 Clock to Center Frequency Ratio Deviation VPin12 = 5V or 0V fCLK = 1 MHz ±0.2 ±0.8 ±0.8 ±0.2 ±0.8 % Q Error (MAX) (Note 4) Q = 10, Mode 1 VPin12 = 5V or 0V fCLK = 1 MHz ±0.5 ±5 ±6 ±0.5 ±6 % HOBP Bandpass Gain at f0 fCLK = 1 MHz 0 ±0.4 ±0.4 0 ±0.4 dB HOLP DC Lowpass Gain R1 = R2 = 10k 0 ±0.2 ±0.2 0 ±0.2 dB fCLK = 250 kHz VOS1 DC Offset Voltage (Note 5) fCLK = 250 kHz ±5.0 ±15 ±15 ±5.0 ±15 mV VOS2 DC Offset Voltage (Note 5) fCLK = 250 kHz SA/B = V + ±30 ±80 ±80 ±30 ±80 mV SA/B = V − ±15 ±70 ±70 ±15 ±70 mV VOS3 DC Offset Voltage (Note 5) fCLK = 250 kHz ±15 ±40 ±60 ±15 ±60 mV Crosstalk (Note 6) A Side to B Side or −60 −60 dB B Side to A Side Output Noise (Note 12) fCLK = 250 kHz N 40 40 20 kHz Bandwidth BP 320 320 µV 100:1 Mode LP 300 300 Clock Feedthrough (Note 13) fCLK = 250 kHz 100:1 Mode 6 6 mV VOUT Minimum Output RL = 5k +4.0 ±3.8 ±3.7 +4.0 ±3.7 V Voltage Swing (All Outputs) −4.7 −4.7 RL = 3.5k +3.9 +3.9 V (All Outputs) −4.6 −4.6 GBW Op Amp Gain BW Product 5 5 MHz SR Op Amp Slew Rate 20 20 V/µs Isc Maximum Output Short Source (All Outputs) 12 12 mA Circuit Current (Note 7) Sink 45 45 mA www.national.com 2 |
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