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LMF60 数据表(PDF) 9 Page - National Semiconductor (TI) |
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LMF60 数据表(HTML) 9 Page - National Semiconductor (TI) |
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9 / 20 page  Crosstalk Test Circuits From Filter to Op-Amps TLH9294 – 6 From Either Op-Amp to Filter Output TLH9294 – 7 Pin Description (Pin Numbers) Pin Description FILTER OUT (3) The output of the lowpass filter will typi- cally swing to within 1V of each supply rail FILTER IN (8) The input to the lowpass filter To mini- mize gain errors the source impedance that drives this input should be less than 2k (See Section 14) For single supply operation the input signal must be bi- ased to mid-supply or AC coupled VOSADJ (7) This pin is used to adjust the DC offset of the filter output if not used it must be tied to the AGND potential (See Section 13) AGND (5) The analog ground pin This pin sets the DC bias level for the filter section and the noninverting input of Op-Amp 1 and must be tied to the system ground for split supply operation or to mid-sup- ply for single supply operation (See Sec- tion 12) When tied to mid-supply this pin should be well bypassed VO1(4) VO1 is the output and INV1 is the invert- INV1 (13) ing input of Op-Amp 1 The non-invert- ing input of this Op-Amp is internally connected to the AGND pin VO2(2) VO2 is the output INV2 is the inverting INV2 (14) input and NINV2 is the non-inverting in- NINV2 (1) put of Op-Amp 2 Va (6) Vb (10) The positive and negative supply pins The total power supply range is 4V to 14V Decoupling these pins with 01 mF capacitors is highly recommended Pin Description CLK IN (9) A CMOS Schmitt-trigger input to be used with an external CMOS logic level clock Also used for self-clocking Schmitt-trigger oscillator (See Section 11) CLK R (11) A TTL logic level clock input when in split supply operation (g2V to g7V) and L Sh tied to system ground This pin be- comes a low impedance output when LSh is tied to Vb Also used in conjunc- tion with the CLK IN pin for self clocking Schmitt-trigger oscillator (See Section 11) LSh (12) Level shift pin selects the logic thresh- old levels for the desired clock When tied to Vb it enables an internal TRI- STATE buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt-trigger input and making the CLK R pin a low impedance output When the voltage level at this input ex- ceeds 25% (Va b Vb) a V b the in- ternal TRI-STATE buffer is disabled al- lowing the CLK R pin to become the clock input for the internal clock level shift stage The CLK R threshold level is now 2V above the voltage applied to the LSh pin Driving the CLK R pin with TTL logic levels can be accomplished through the use of split supplies and by tying the LSh pin to system ground http www nationalcom 9 |
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