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LMF60 数据表(PDF) 10 Page - National Semiconductor (TI) |
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LMF60 数据表(HTML) 10 Page - National Semiconductor (TI) |
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10 / 20 page ![]() 10 LMF60 Application Hints The LMF60 is comprised of a non-inverting unity gain low- pass sixth-order Butterworth switched capacitor filter sec- tion and two undedicated CMOS Op-Amps The switched- capacitor topology makes the cutoff frequency (where the gain drops 301 dB below the DC gain) a direct ratio (1001 or 501) of the clock frequency supplied to the lowpass filter Internal integrator time constants set the filter’s cutoff fre- quency The resistive element of these integrators is actual- ly a capacitor which is ‘‘switched’’ at the clock frequency (for a detailed discussion see Input Impedance section) Varying the clock frequency changes the value of this resis- tive element and thus the time constant of the integrators The clock to cutoff frequency ratio (fCLK fC) is set by the ratio of the input and feedback capacitors in the integrators The higher the clock to cutoff frequency ratio (or the sam- pling rate) the closer the approximation is to the theoretical Butterworth response The LMF60 is available in fCLK fC ratios of 501 (LMF60-50) or 1001 (LMF60-100) 11 CLOCK INPUTS The LMF60 has a Schmitt-trigger inverting buffer which can be used to construct a simple RC oscillator The oscillator frequency is dependent on the buffer’s threshold levels as well as on the resistorcapacitor tolerance (See Figure 1 ) Schmitt-trigger threshold voltage levels can vary significant- ly causing the RC oscillator’s frequency to vary greatly from part to part Where accuracy in fC is required an external clock can be used to drive the CLK R input of the LMF60 This input is TTL logic level compatible and also presents a very light load to the external clock source (E2 mA) with split sup- plies and LSh tied to system ground The logic level is pro- grammed by the voltage applied to level shift (LSh) pin (See the Pin Description for LSh pin) 12 POWER SUPPLY BIASING The LMF60 can be biased from a single supply or dual split supplies The split supply mode shown in Figures 2 and 3 is the most flexible and easiest to implement As discussed earlier split supplies g2V to g7V will enable the use of TTL or CMOS clock logic levels Figure 4 shows two schemes for single supply biasing In this mode only CMOS clock logic levels can be used TLH9294 – 8 fCLK e 1 RC In VCCbVTb VCC b VTa J VTa VTb ( Typically for VCC e Va b Vb e 10V fCLK e 1 137 RC FIGURE 1 Schmitt Trigger RC Oscillator http www nationalcom 10 |
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