POWER DISSIPATION

Follow these steps to determine the power consumption of

the LMH6718:

1. Calculate the quiescent (no-load) power: P

amp

=I

CC

(V

2. Calculate the RMS power at the output stage: P

−V

current across the external load.

3. Calculate the total RMS power: P

mum power that the SOIC, package can dissipate at a given

temperature is illustrated in Figure 12. The power derating

curve for any LMH6718 package can be derived by utilizing

the following equation:

where

T

θ

given package (˚C/W)

LAYOUT CONSIDERATIONS

A proper printed circuit layout is essential for achieving high

frequency performance. National provides evaluation boards

for the LMH6718 (CLC730036-SOIC) and suggests their use

as a guide for high frequency layout and as an aid for device

testing and characterization.

General layout and supply bypassing play major roles in high

frequency performance. Follow the steps below as a basis

for high frequency layout:

•

Include 6.8µF tantalum and 0.1µF ceramic capacitors on

both supplies.

•

Place the 6.8µF capacitors within 0.75 inches of the

power pins.

•

Place the 0.1µF capacitors less than 0.1 inches from the

power pins.

•

Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance.

•

Minimize all trace lengths to reduce series inductances.

•

Use flush-mount printed circuit board pins for prototyping,

never use high profile DIP sockets.

EVALUATION BOARD INFORMATION

A datasheet is available for the CLC730036 evaluation

board. The evaluation board data sheets provide:

•

Evaluation board schematics

•

Evaluation board layouts

•

General information about the boards

The evaluation boards are designed to accommodate dual

supplies. The boards can be modified to provide single

supply operation. For best performance; 1) do not connect

the unused supply, 2) ground the unused supply pin.

SPECIAL EVALUATION BOARD CONSIDERATION FOR

THE LMH6718

To optimize off-isolation of the LMH6718, cut the R

the CLC730036 evaluation boards. This cut minimizes ca-

pacitive feedthrough between the input and the output. Fig-

ure 13 shows where to cut both evaluation boards for im-

proved off-isolation.

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FIGURE 11. Transmission Line Matching

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FIGURE 12. Power Derating Curve

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FIGURE 13. Evaluation Board Changes

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