LPC2129 datasheet(19/34 Pages) PHILIPS

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Philips Semiconductors

LPC2119/LPC2129

Single-chip 16/32-bit microcontrollers

Product data

Rev. 03 — 22 December 2004

19 of 34

9397 750 13146

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.

• The I2C bus may be used for test and diagnostic purposes.

6.15 SPI serial I/O controller

The LPC2119/LPC2129 each contain two SPIs. The SPI is a full duplex serial

interface, designed to be able to handle multiple masters and slaves connected to a

given bus. Only a single master and a single slave can communicate on the interface

during a given data transfer. During a data transfer the master always sends a byte of

data to the slave, and the slave always sends a byte of data to the master.

6.15.1

Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.16 General purpose timers

The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally

generate interrupts or perform other actions at speciﬁed timer values, based on four

match registers. It also includes four capture inputs to trap the timer value when an

input signal transitions, optionally generating an interrupt. Multiple pins can be

selected to perform a single capture or match function, providing an application with

‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.16.1

Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

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