MPC855 datasheet(3/76 Pages) MOTOROLA

3 / 76 page

MOTOROLA

MPC860 Family Hardware Speciﬁcations

Features

– Caches are physically addressed, implement a least recently used (LRU)

replacement algorithm, and are lockable on a cache block basis.

— Instruction and data caches are two-way, set-associative, physically addressed,

LRU replacement, and lockable on-line granularity.

— MMUs with 32-entry TLB, fully associative instruction, and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16

virtual address spaces and 16 protection groups

— Advanced on-chip-emulation debug mode

•

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

•

32 address lines

•

Operates at up to 80 MHz

•

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 15 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and

other memory devices.

— DRAM controller programmable to support most size and speed memory

interfaces

— Four CAS lines, four WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte to 256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

MPC855 数据表(PDF) 3 Page - Motorola, Inc

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