PCI7421 datasheet(69/298 Pages) TI

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3−13

Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command

bit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledge

reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data

transfers. The SCL signal remains driven by the PCI7x21/PCI7x11 master.

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Sb6

b3 b2 b1 b0

Slave Address

S/P = Start/Stop Condition

M = Master Acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Start

Restart

R/W

A = Slave Acknowledgement

Stop

Figure 3−10. Serial-Bus Protocol—Byte Read

Figure 3−11 illustrates EEPROM interface doubleword data collection protocol.

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Data Byte 2

Data Byte 1

Data Byte 0

M = Master Acknowledgement

S/P = Start/Stop Condition

A = Slave Acknowledgement

Data Byte 3

001

Restart

R/W

Slave Address

Start

Figure 3−11. EEPROM Interface Doubleword Data Collection

3.6.4

Serial-Bus EEPROM Application

When the PCI bus is reset and the serial-bus interface is detected, the PCI7x21/PCI7x11 controller attempts to read

the subsystem identification and other register defaults from a serial EEPROM.

This format must be followed for the PCI7x21/PCI7x11 controller to load initializations from a serial EEPROM. All bit

fields must be considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010 000b by the PCI7x21/PCI7x11 controller. All hardware

address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip

in the sample application (Figure 3−11) assumes the 1010b high-address nibble. The lower three address bits are

terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

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