STR71XF datasheet(24/49 Pages) STMICROELECTRONICS

24 / 49 page

STR71xF - INTRODUCTION

24/49

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to

Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is

PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column

which specifies whether the pull-up or pull-down is enabled at reset

2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must

be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,”

on page 26) to be used by the External Memory Interface.

P0.1/S0.MOSI/

U3.RX

I/O pu

CT X4mA X

Port 0.1

BSPI0: Master

out/Slave in data

UART3: Receive Data in-

put

Note: Programming AF function selects

UART by default. BSPI must be enabled by

SPI_EN bit in the BOOTCR register.

P0.2/

S0.SCLK/

I1.SCL

I/O pu

CT X4mA X

Port 0.2

BSPI0: Serial

Clock

I2C1: Serial clock

Note: Programming AF function selects I2C

by default. BSPI must be enabled by SPI_EN

bit in the BOOTCR register.

P0.3/S0.SS/

I1.SDA

I/O pu

4mA X

Port 0.3

SPI0: Slave Se-

lect input active

low.

I2C1: Serial Data

Note: Programming AF function selects I2C

by default. BSPI must be enabled by SPI_EN

bit in the BOOTCR register.

P0.4/S1.MISO

I/O pu

4mA X

Port 0.4

SPI1: Master in/Slave out data

VSS18

Stabilisation for main voltage regulator.

V18

Stabilisation for main voltage regulator. Requires exter-

nal capacitors of at least 10µF + 33nF between V18 and

VSS18. See Figure 5.

VSS

Ground voltage for digital I/Os

P0.5/S1.MOSI

I/O pu

4mA X

Port 0.5

SPI1: Master out/Slave In data

P0.6/S1.SCLK

I/O pu

CT X 4mA X

Port 0.6

SPI1: Serial Clock

P0.7/S1.SS

I/O pu

4mA X

Port 0.7

SPI1: Slave Select input active low

P0.8/U0.RX/

U0.TX

I/O pd CT X4mA T

Port 0.8

UART0: Receive

Data input

UART0: Transmit data

output.

Note: This pin may be used for single wire UART (half

duplex) if programmed as Alternate Function Output.

The pin will be tri-stated except when UART transmis-

sion is in progress

P0.9/U0.TX/

BOOT.0

I/O pd CT

4mA X

Port 0.9

Select Boot Con-

figuration input

UART0: Transmit data

output

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Input

Output

Main

function

(after

reset)

Alternate function

STR71XF 数据表(PDF) 24 Page - STMicroelectronics

STR71XF 数据表(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载

链接网址

STR71XF 数据表(PDF) 24 Page - STMicroelectronics

STR71XF 数据表(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表 下载

链接网址

数据表下载