LP3982 datasheet(9/12 Pages) NSC

9 / 12 page

Application Information (Continued)

The delay time for the application of Figure 5 is set as

follows:

The application is set for a reset delay time of 8.8ms. Note

that the comparator should have high impedance inputs so

as to not load down the V

REF at the CC pin of the LP3982.

Shutdown

The LP3982 goes into sleep mode when the SHDN pin is in

a logic low condition. During this condition, the pass transis-

tor, error amplifier, and bandgap are turned off, reducing the

supply current to 1nA typical. The maximum guaranteed

voltage for a logic low at the SHDN pin is 0.4V. A minimum

guaranteed voltage of 2V at the SHDN pin will turn the

LP3982 back on. The SHDN pin may be directly tied to V

IN to

keep the part on. The SHDN pin may exceed V

IN but not the

ABS MAX of 6.5V.

Figure 6 shows an application that uses the SHDN pin. It

detects when the battery is too low and disconnects the load

by turning off the regulator. A micropower comparator

(LMC7215) and reference (LM385) are combined with resis-

tors to set the minimum battery voltage. At the minimum

battery voltage, the comparator output goes low and tuns off

the LP3982 and corresponding load. Hysteresis is added to

the minimum battery threshold to prevent the battery’s re-

covery voltage from falsely indicating an above minimum

condition. When the load is disconnected from the battery, it

automatically increases in terminal voltage because of the

reduced IR drop across its internal resistance. The Minimum

battery detector of figure 6 has a low detection threshold

LT) of 3.6V that corresponds to the minimum battery volt-

age. The upper threshold (V

UT) is set for 4.6V in order to

exceed the recovery voltage of the battery.

Resistor value for V

UT and VLT are determined as follows:

(The application of figure 6 used a G

T of 5µ mho)

The above procedure assumes a rail-to-rail output compara-

tor. Essentially, R

2 is in parallel with R1 prior to reaching the

lower threshold, then R

2 becomes parallel with R3 for the

upper threshold. Note that the application requires rail-to-rail

input as well.

The resistor values shown in Figure 6 are the closest prac-

tical to calculated values.

Fast Start-up

The LP3982 provides fast start-up time for better system

efficiency. The start-up speed is maintained when using the

optional noise bypass capacitor. An internal 500µA current

source charges the capacitor until it reaches about 90% of its

final value.

20036921

FIGURE 5. Power on Delayed Reset Application

20036902

FIGURE 6. Minimum Battery Detector that Disconnects

the Load Via the SHDN Pin of the LP3982

LP3982 数据表(PDF) 9 Page - National Semiconductor (TI)

LP3982 数据表(HTML) 9 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

数据表下载