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FT51AL-R 数据表(PDF) 41 Page - Future Technology Devices International Ltd. |
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FT51AL-R 数据表(HTML) 41 Page - Future Technology Devices International Ltd. |
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41 / 43 page  Copyright © Future Technology Devices International Limited 41 FT51A Advanced MCU with 8051 Compatible Core IC Datasheet Version 1.5 Doc ument N o.: FT _000877 C learance N o.: FT DI#420 Register Address Register Name Description (0xB8) DMA_IO_ADDR_L_1 DMA IO Addr Register (Lower Bits) (0xB9) DMA_IO_ADDR_U_1 IO DMA IO Addr Register (Upper Bits) (0xBA) DMA_TRANS_CNT_L_1 IO DMA Transfer Byte Count Register (Lower Bits) (0xBB) DMA_TRANS_CNT_U_1 IO DMA Transfer Byte Count Register (Upper Bits) (0xBC) DMA_CURR_CNT_L_1 IO DMA Current Byte Count Register (Lower Bits) (0xBD) DMA_CURR_CNT_U_1 IO DMA Current Byte Count Register (Upper Bits) (0xBE) DMA_FIFO_DATA_1 IO DMA FIFO DATA (0xBF) DMA_AFULL_TRIGGER_1 IO DMA Almost Full Flag Trigger Value (0xC0) DMA_CONTROL_2 DMA Control Register (0xC1) DMA_ENABLE_2 IO DMA Enable Register (0xC2) DMA_IRQ_ENA_2 DMA IO Interrupt Enable & Control Register (0xC3) DMA_IRQ_2 DMA IO Interrupt Register (0xC4) DMA_SRC_MEM_ADDR_L_2 DMA IO Source Mem Addr Register (Lower Bits) (0xC5) DMA_SRC_MEM_ADDR_U_2 DMA IO Source Mem Addr Register (Upper Bits) (0xC6) DMA_DEST_MEM_ADDR_L_2 DMA IO Destination Mem Addr Register (Lower Bits) (0xC7) DMA_DEST_MEM_ADDR_U_2 DMA IO Destination Mem Addr Register (Upper Bits) (0xC8) DMA_IO_ADDR_L_2 DMA IO Addr Register (Lower Bits) (0xC9) DMA_IO_ADDR_U_2 IO DMA IO Addr Register (Upper Bits) (0xCA) DMA_TRANS_CNT_L_2 IO DMA Transfer Byte Count Register (Lower Bits) (0xCB) DMA_TRANS_CNT_U_2 IO DMA Transfer Byte Count Register (Upper Bits) (0xCC) DMA_CURR_CNT_L_2 IO DMA Current Byte Count Register (Lower Bits) (0xCD) DMA_CURR_CNT_U_2 IO DMA Current Byte Count Register (Upper Bits) (0xCE) DMA_FIFO_DATA_2 IO DMA FIFO DATA (0xCF) DMA_AFULL_TRIGGER_2 IO DMA Almost Full Flag Trigger Value (0xD0) DMA_CONTROL_3 DMA Control Register (0xD1) DMA_ENABLE_3 IO DMA Enable Register (0xD2) DMA_IRQ_ENA_3 DMA IO Interrupt Enable & Control Register (0xD3) DMA_IRQ_3 DMA IO Interrupt Register (0xD4) DMA_SRC_MEM_ADDR_L_3 DMA IO Source Mem Addr Register (Lower Bits) (0xD5) DMA_SRC_MEM_ADDR_U_3 DMA IO Source Mem Addr Register (Upper Bits) (0xD6) DMA_DEST_MEM_ADDR_L_3 DMA IO Destination Mem Addr Register (Lower Bits) (0xD7) DMA_DEST_MEM_ADDR_U_3 DMA IO Destination Mem Addr Register (Upper Bits) (0xD8) DMA_IO_ADDR_L_3 DMA IO Addr Register (Lower Bits) (0xD9) DMA_IO_ADDR_U_3 IO DMA IO Addr Register (Upper Bits) (0xDA) DMA_TRANS_CNT_L_3 IO DMA Transfer Byte Count Register (Lower Bits) (0xDB) DMA_TRANS_CNT_U_3 IO DMA Transfer Byte Count Register (Upper Bits) (0xDC) DMA_CURR_CNT_L_3 IO DMA Current Byte Count Register (Lower Bits) |
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