AD8651/AD8652

Rev. B | Page 16 of 20

oscillations. With the AD8651, additional input damping is

required for stability with capacitive loads greater than 47 pF

with direct input to output feedback (see the next section).

Output Capacitance

When using high speed amplifiers, it is important to consider

the effects of the capacitive loading on the amplifier’s stability.

Capacitive loading interacts with the output impedance of the

amplifier, causing reduction of the BW as well as peaking and

ringing of the frequency response. To reduce the effects of the

capacitive loading and allow higher capacitive loads, there are

two commonly used methods:

series with the output to isolate the load capacitor from the

amplifier’s output. Heavy capacitive loads can reduce the phase

margin of an amplifier and cause the amplifier response to peak

or become unstable. The AD8651 is able to drive up to 47 pF in

a unity gain buffer configuration without oscillation or external

compensation. However, if an application will require a higher

capacitive load drive when the AD8651 is in unity gain, then

the use of external isolation networks can be used. The effect

produced by this resistor is to isolate the op amp output from

the capacitive load. The required amount of series resistance has

been tabulated in Table 5 for different capacitive load. While

this technique will improve the overall capacitive load drive for

the amplifier, its biggest drawback is that it reduces the output

swing of the overall circuit.

+

–

V–

0

0

0

3

2

U1

RL

CL

AD8651

Figure 55. Driving Large Capacitive Loads

Table 5. Optimum Values for Driving Large Capacitive Loads

CL

100 pF

50 Ω

500 pF

35 Ω

1.0 nF

25 Ω

2) Another way to stabilize an op amp driving a large capacitive

load is to use a snubber network, as shown in Figure 56.

Because there is not any isolation resistor in the signal path, this

method has the significant advantage of not reducing the output

capacitive load drive ranging from 50 pF to 1 nF was chosen.

+

–

V–

200mV

RL

CL

V–

AD8651

Figure 56. Snubber Network

Settling Time

The settling time of an amplifier is defined as the time it takes

for the output to respond to a step change of input and enter

and remain within a defined error band, as measured relative to

the 50% point of the input pulse. This parameter is especially

important in measurements and control circuits where amplifi-

ers are used to buffer A/D inputs or DAC outputs. The design of

the AD8651 combines a high slew rate and a wide gain band-

width product to produce an amplifier with very fast settling

time. The AD8651 is configured in the noninverting gain of 1

with a 2 V p-p step applied to its input. The AD8651 has a

settling time of about 130 ns to 0.01% (2 mV). The output is

monitored with a 10×, 10 M, 11.2 pF scope probe.

THD Readings vs. Common-Mode Voltage

Total harmonic distortion of the AD8651 is well below 0.0004%

with any load down to 600 Ω. The distortion is a function of the

circuit configuration, the voltage applied, and the layout, in

addition to other factors. The AD8651 outperforms its

competitor for distortion, especially at frequencies below

20 kHz, as shown in Figure 57.

0.0001

0.0002

0.0005

0.001

0.002

0.005

0.01

0.02

0.05

0.1

FREQUENCY (Hz)

AD8651

20

50

100

500

20k

5k

2k

1k

OPA350

Figure 57. Total Harmonic Distortion

+

–

2V p-p

47pF

600

Ω

3.5V

–1.5V

AD8651

Figure 58. THD + N Test Circuit