Functional Description

Both the MM5450 and the MM5451 are specifically de-

signed to operate 4- or 5-digit alphanumeric displays with

minimal interface with the display and the data source Seri-

al data transfer from the data source to the display driver is

accomplished with 2 signals serial data and clock Using a

format of a leading ‘‘1’’ followed by the 35 data bits allows

data transfer without an additional load signal The 35 data

bits are latched after the 36th bit is complete thus providing

non-multiplexed direct drive to the display Outputs change

only if the serial data bits differ from the previous time Dis-

play brightness is determined by control of the output cur-

rent for LED displays A 0001 capacitor should be connect-

ed to brightness control pin 19 to prevent possible oscilla-

tions

A block diagram is shown in

DATA ENABLE is used instead of the 35th output The

DATA ENABLE input is a metal option for the MM5450 The

output current is typically 20 times greater than the current

into pin 19 which is set by an external variable resistor

There is an internal limiting resistor of 400

X nominal value

‘‘1’’ precedes the 35 bits of data At the 36th clock a LOAD

signal is generated synchronously with the high state of the

clock which loads the 35 bits of the shift registers into the

latches At the low state of the clock a RESET signal is

generated which clears all the shift registers for the next set

of data The shift registers are static master-slave configura-

tion There is no clear for the master portion of the first shift

register thus allowing continuous operation

There must be a complete set of 36 clocks or the shift regis-

ters will not clear

When the chip first powers ON an internal power ON reset

signal is generated which resets all registers and all latches

The START bit and the first clock return the chip to its nor-

mal operation

1 is the first bit following the start bit and it will appear on pin

18 A logical ‘‘1’’ at the input will turn on the appropriate

LED

and DATA ENABLE A max clock frequency of 05 MHz is

assumed

For applications where a lesser number of outputs are used

it is possible to either increase the current per output or

equation can be used for calculations

where

The above equation was used to plot

Figure 7

TLF6136 – 4

FIGURE 3

4