 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AT89C51CC03U-RDTIM 数据表(PDF) 115 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT89C51CC03U-RDTIM 数据表(HTML) 115 Page - ATMEL Corporation |
|
|
115 / 195 page  115 AT89C51CC03 4182I–CAN–06/05 Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers 1 Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis- abled with the ENA bit of the CANGCON register set to 0. See Figure 52. No default value after reset. 76 543 210 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6-1 BRP5:0 Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. Tscl = BRP[5..0] + 1 Fcan |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
