AT89C51CC03U-RDTIM datasheet(139/195 Pages) ATMEL

139 / 195 page

139

AT89C51CC03

4182I–CAN–06/05

Reset Value = 0001 0100b

Not bit addressable

Serial Peripheral Status Register

and Control (SPSCR)

The Serial Peripheral Status Register contains flags to signal the following conditions:

•

Data transfer complete

•

Write collision

•

Inconsistent logic level on SS pin (mode fault error)

Table 93. SPSCR Register

SPSCR - Serial Peripheral Status and Control register (0D5H)

3CPOL

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle state.

2CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

SPR1

SPR2 SPR1

SPR0 Serial Peripheral Rate

Invalid

FCLK PERIPH /4

FCLK PERIPH /8

FCLK PERIPH /16

FCLK PERIPH /32

FCLK PERIPH /64

FCLK PERIPH /128

Invalid

SPR0

Bit Number

Bit Mnemonic

Description

543

210

SPIF

OVR

MODF

SPTE

UARTM

SPTEIE

MODFIE

Bit

Number

Bit

Mnemonic Description

7SPIF

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

This bit is cleared when reading or writing SPDATA after reading SPSCR.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5OVR

Overrun Error Flag

- Set by hardware when a byte is received whereas SPIF is set (the previous

received data is not overwritten).

- Cleared by hardware when reading SPSCR

AT89C51CC03U-RDTIM 数据表(PDF) 139 Page - ATMEL Corporation

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